Setup panics if RX FIFO is not empty

[jannic]

As noticed here, setup will panic if self.rx is not empty. This could happen after an error condition in finish.

[ithinuel]

If finish is called while an error condition has been detected, resume_after_error flushes the tx fifo and restarts the SM, and wait_idle waits until the SM has stalled on the first OUT instruction.
stop only sends instructions and therefore cannot generate an error condition (=no ack).

In case of error during a read operation, the data in the buffer are unreliable, there's no feed back to caller as to how many bytes were received before the error. A caller may rely on pattern matching to detect that? 🤷

read should empty the rx fifo before exiting to drain all the success fully clocked in bytes.
write already flushes the RX firo before exiting, as any rx bytes are to be ignored.

This'd effectively ensure that finish is always called with an empty RX FIFO (possibly in case of error, with a non-empty TX fifo to be drained by resume_after_error).

[ithinuel]

This should be fixed by #17.