Repository containing the "Introduction to Very Large Scale Integration Design" course from the 2026 Argentine School for Micro-nano Electronics, Technology and Applications
See docs/GETTING_STARTED.md for setup instructions.
See docs/STUDENT_WORKFLOW.md for the development workflow.
See docs/DESIGN_SPECIFICATIONS.md for detailed design specifications.
This repository contains the design and verification flow for a 4-bit counter implemented in the IHP SG13G2 130nm PDK. The project is structured to allow multiple student groups to work collaboratively on different blocks of the counter.
- Container: hpretl/iic-osic-tools (via podman & distrobox)
- Schematics: xschem
- Simulation: ngspice
- Characterization: CACE
- Layout: KLayout
- PDK: IHP SG13G2 130nm
.
├── design/ # Design files
│ ├── blocks/ # Individual counter blocks (assigned to student groups)
│ └── top/ # Top-level counter integration
├── verification/ # Verification and testbenches
│ ├── testbenches/ # ngspice testbenches
│ └── vectors/ # Test vectors
├── scripts/ # Automation and flow scripts
├── tools-config/ # Tool configuration files
├── examples/ # Example implementations and tutorials
└── docs/ # Documentation and guidelines
The 4-bit counter consists of the following blocks:
- D Flip-Flop (DFF) - Basic storage element
- XOR Gate - Toggle logic
- AND Gate - Ripple carry logic
- Counter Stage - Single bit counter stage
- Top-Level Counter - 4-bit counter integration
Each student group will be assigned one or more blocks to design, simulate, characterize, and layout.
Student groups will be assigned blocks through GitHub Issues. See docs/GROUP_ASSIGNMENTS.md for details.
Please follow the workflow described in docs/STUDENT_WORKFLOW.md. Each group should:
- Work in their assigned block directory
- Create feature branches for their work
- Submit pull requests for review
- Ensure their design passes verification before submitting