This project demonstrates the transistor-level implementation of a 4-bit Ripple Carry Adder (RCA) using CMOS logic in Cadence Virtuoso with the 90 nm GPDK technology. The design is simulated using Spectre for transient analysis and verified for functional correctness.
- Cadence Virtuoso – Schematic design and simulation
- GPDK 90nm – Process Design Kit
- Spectre Simulator – For transient analysis
| Folder | Description |
|---|---|
schematics/ |
CMOS schematics of and, schematics of xor, full adder and RCA |
symbols/ |
CMOS symbols of full adder and RCAs |
testbench/ |
CMOS testbench of full adder and RCAs |
output/ |
Transient waveforms and timing results |
- Designed basic CMOS gates (XOR, AND, OR).
- Built a Full Adder using CMOS logic at transistor level.
- Cascaded four Full Adders to form a 4-bit Ripple Carry Adder.
- Performed Transient Analysis using Spectre.
- Verified output propagation and correctness.
Transient Waveform:
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Specification & Logic Design
- Defined the functionality of a 4-bit Ripple Carry Adder using four cascaded full adders.
- Derived Boolean expressions for Sum and Carry outputs.
-
Transistor-Level Schematic Design
- Designed basic CMOS logic gates (XOR, AND, OR) using GPDK 90nm technology.
- Built a Full Adder cell at the transistor level using these gates.
- Created a hierarchical schematic connecting four Full Adders to form the RCA.
-
Simulation
- Configured testbench with input vectors for all combinations.
- Performed Transient Analysis in Spectre to verify correct logical operation and timing
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Result Verification
- Observed correct propagation of carry and valid Sum/Cout outputs.
- Captured transient waveforms (
waveform_1.jpg,waveform_2.jpg) confirming the expected performance.
Example output
| Inputs (A3–A0, B3–B0, Cin) | Outputs (S3–S0, Cout) |
|---|---|
| 1010 + 0101 + 0 | 1111, 0 |
| 1111 + 0001 + 0 | 0000, 1 |
- CMOS transistor-level logic design
- Full Adder implementation at device level
- Delay and carry propagation study
- Hierarchical schematic design in Cadence