IEEE-754 Single-Precision Floating-Point Multiplier in SystemVerilog

Institution: Aristotle University of Thessaloniki — Department of Electrical & Computer Engineering
Course: Low-Level Hardware Digital Systems II
Language: SystemVerilog (IEEE 1800-2012)
Simulator: Questa-Intel FPGA Starter Edition 2021.2

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Overview

This repository contains the RTL design, functional verification, and formal property checking of a 32-bit IEEE-754 single-precision floating-point multiplier. The design is implemented in synthesizable SystemVerilog and features a single-stage pipeline, support for six rounding modes, and dedicated handling for corner cases (NaNs, Infinities, Denormals).

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Architecture & Datapath

The multiplier is partitioned into distinct combinatorial submodules separated by a pipeline register stage.

1. Sign & Exponent Logic — Evaluates the XOR of the input signs and calculates the intermediate biased exponent (exp_a + exp_b - 127).
2. Mantissa Multiplication — Multiplies the 24-bit mantissas (including the hidden 1) to generate a 48-bit product.
3. Normalization (normalize_mult) — Checks bit 47 of the product. If set, performs a 1-bit right shift, increments the exponent, and extracts the guard and sticky bits.
4. Pipeline Stage — A single always_ff @(posedge clk) block registers the sign, normalized exponent, mantissa, guard/sticky bits, and rounding mode.
5. Rounding (round_mult) — Applies one of six IEEE rounding policies based on the guard and sticky bits. Outputs a 25-bit mantissa to account for potential carry-out.
6. Exception Handling (exception_mult) — Evaluates original operands to handle special values (Zero, Infinity, NaN) and normalizes any post-rounding overflow/underflow, driving the final 32-bit output and the 8-bit status vector.

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Status Flag Vector

Bit	Flag	Description
0	zero_f	Result is ±0
1	inf_f	Result is ±Infinity
2	nan_f	Invalid operation (e.g., 0 × Inf) resulting in NaN
3	tiny_f	Underflow
4	huge_f	Overflow
5	inexact_f	Result is not exact (guard or sticky bit asserted)
6–7	—	Unused / Reserved to 0

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Verification Strategy

Functional Testing

The DUT is verified against a DPI-compatible SystemVerilog software reference model (multiplication.sv) using a self-checking testbench (tb_fp_mult.sv). The simulation is split into two phases:

• Random Testing: 120 iterations utilizing $urandom() constraints across all six rounding modes.
• Corner-Case Matrix: 864 directed tests evaluating all 144 valid operand-pair combinations of special values (Zero, Infinity, Normal, Denormal, QNaN, SNaN) across all rounding modes.

Property Checking (SVA)

Assertions are bound non-intrusively to the DUT wrapper using the bind construct.

• Immediate Assertions: Verify mutual exclusion of status flags (e.g., zero_f and inf_f never assert simultaneously).
• Concurrent Assertions: Validate temporal logic and expected output constraints. For example, ensuring that a nan_f assertion correlates with an Inf × 0 input pattern exactly two clock cycles prior ($past(..., 2)).

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File Manifest

File	Location	Description
fp_mult_top.sv	exercise1/	Top-level wrapper — instantiates fp_mult as multiplier. Bind target.
fp_mult.sv	exercise1/	Datapath integrating submodules and the pipeline register stage.
normalize_mult.sv	exercise1/	Combinational logic for truncation, shifting, and guard/sticky extraction.
round_mult.sv	exercise1/	Combinational logic for the 6 rounding modes (IEEE_near, IEEE_zero, etc.)
exception_mult.sv	exercise1/	Corner-case handling, overflow/underflow checks, and status flag generation.
tb_fp_mult.sv	exercise2/	Self-checking testbench for random and directed verification.
multiplication.sv	exercise2/	Software reference model (CU-scope function) returning golden values.
fp_mult_assertions.sv	exercise3/	Immediate and concurrent SVA properties with bind statements.

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How to Run

All commands are entered in the Questa transcript window from the FP_Multiplier_HW2/ directory.

# 1. Create the working library
vlib work

# 2. Compile RTL modules and top-level wrapper (exercise1/)
vlog -sv +acc \
    exercise1/exception_mult.sv \
    exercise1/normalize_mult.sv \
    exercise1/round_mult.sv \
    exercise1/fp_mult.sv \
    exercise1/fp_mult_top.sv

# 3. Compile assertions (MFCU required for bind resolution)
vlog -sv +acc -mfcu -cuname assertions_unit exercise3/fp_mult_assertions.sv

# 4. Compile testbench
#    (multiplication.sv is `included inside tb_fp_mult.sv — no separate step needed)
vlog -sv +acc exercise2/tb_fp_mult.sv

# 5. Load simulation with full visibility
vsim work.tb_fp_mult -L work -voptargs=+acc

# 6. (Optional) log transcript and add a signal of interest
transcript file my_full_simulation.log
add wave -position end sim:/tb_fp_mult/dut/multiplier/round_module/long_mantis

# 7. Run simulation
run 40000ns

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License

This repository is submitted as academic coursework for the Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki. Source code is shared for educational reference.