OpenTitan Flash Ctrl IP block

Cryptographically Secure Random Number Generator (CSRNG)

System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

Analog to Digital Converter Control Interface

OpenTitan Rv Core Ibex IP block

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

SRAM memory controller

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

This document specifies the OTP MACRO hardware IP functionality.

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

I2C controller

OpenTitan Prim Generic IP block

ROM controller (rom_ctrl) is the connection between the chip and its ROM

OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support

TL-UL is a lightweight (uncached) bus that combines the point-to-point split-transaction features of the powerful TileLink (or AMBA AXI) 5-channel bus without the high pin-count overhead.

RISC-V timer module provides a configurable number of 64-bit counters

OpenTitan Prim Xilinx Ultrascale IP block

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Entropy Source: interface to an external physical random noise generator

RISC-V Debug System wrapper functionality